The present invention relates in general to integrated circuits, and in particular to method and circuitry for removing undesirable dc offset in circuits of the type used in communication devices.
In electronic circuitry, noise, component mismatches and other types of imbalances often introduce a deviation in the intended value of a circuit reference signal. The amount of this deviation in the reference signal is commonly referred to as an offset signal. The impact of such an offset on the dc performance of a circuit is typically measured by referring its effects to the input of the circuit. During normal operation of a circuit, any offset signals (e.g., offset current or offset voltage) are indistinguishable from, and are processed similar to, the input signal. If, for example, the circuit amplifies the input signal, the offset signal is similarly amplified. This often leads to undesirable effects such as circuit saturation and potentially circuit malfunction.
Some circuits are more susceptible to the adverse effects of offset signals. For example, integrated circuits used in wireless communication devices are often required to perform signal processing in environments that are very sensitive to the introduction of noise and offset. In such applications, input signals to a receiver may be very small, on the order of, for example, 10 microvolts. FIG. 1 shows a simplified block diagram of a direct conversion receiver circuit 100 found in wireless communication devices. A radio frequency (RF) input signal is received by an antenna 102 and amplified by a low noise amplifier (LNA) 104. The signal is then applied to a mixer that multiplies the RF signal with a local oscillator signal (LO), and generates an intermediate frequency (IF) signal on line 108. The high frequency sum products of the IF signal is filtered by a low pass filter (LPF) 110, and the low frequency difference components are passed on to a gain block or baseband amplifier 114 to adjust the signal amplitude. An analog-to-digital (A/D) converter 116 digitizes the signal, and a digital signal processor (DSP) 118 processes the data.
Considering the circuit of FIG. 1, a serious dc offset problem arises due to feedback of the LO signal which is typically locally generated and is therefore a very strong signal. The feedback of the LO signal induces a signal on the RF input line 103 which is then amplified by LNA 104, and combined with the LO signal itself in mixer 106. This is commonly referred to as LO leakage. The result of this LO leakage is a dc voltage which appears as a significant dc offset at the output of mixer 106 on line 108. This dc offset passes through LPF 110 and may cause either the baseband amplifier 114 or A/D 116 (or both) to saturate.
Various offset cancellation techniques have been attempted in the past as discussed, for example, in chapter 13, section 13.2.1 of the book xe2x80x9cDesign of Analog CMOS Integrated Circuits,xe2x80x9d by B. Razavi. One approach deploys ac coupling filters to remove the dc component of the signal. For example, an RC high pass filter of the type shown in FIG. 2A may be inserted along the signal path at nodes 108 or 112 to filter out the dc offset signal. This approach, however, has a time constant problem. That is, to preserve input signal information at lower frequencies, the RC time constant of the ac coupling circuit has to be very large. This in turn renders the ac coupling circuit very slow and therefore inadequate to respond to sudden changes in the dc offset, resulting in possible loss of symbol and degradation in bit error rate (BER). A switched-capacitor ac coupler of the type shown in FIG. 2B that can sample changes in dc offset and respond accordingly has been used as an alternative. However, with this and other similar approaches the sampling of the offset can only occur at idle time when no signal is received by the receiver. Therefore, the switched-capacitor ac coupler cannot respond to dc offset changes that may occur while the receiver is processing its signal. This is particularly a problem for those receivers where LNA 104, for example, is designed to have programmable gain that may vary while receiving an input signal. There is therefore a need for an offset reduction technique that addresses problems caused by such circuit and signal conditions.
The present invention provides method and circuitry for dc offset reduction that is effective under varying circuit and signal conditions. Broadly, in one embodiment, the invention first samples and stores the offset signal Vos, and then subtracts Vos from the signal path via a programmable transconductance amplifiers that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique of the present invention is capable of compensating for variations in the magnitude of the offset signal. In another embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.
Accordingly, in one embodiment, the present invention provides a circuit comprising a signal path having an input coupled to receive an input signal; a variable gain circuit coupled to receive the input signal and to generate an output signal at an output terminal; and an offset reduction circuit coupled to the output terminal, wherein, the offset reduction circuit includes a variable gain transconductance amplifier whose gain is adjusted in response to variations in the gain of the variable gain circuit.
In another embodiment, the present invention provides a receiver circuit comprising an input amplifier coupled to receive an input signal; a mixer having a first input coupled to an output of the input amplifier and a second input coupled to receive a local oscillator signal; and an offset reduction circuit coupled at an output of the mixer, wherein the offset reduction circuit includes a transconductance amplifier having a programmable gain adjusted in response to gain variations in the input amplifier or the mixer.
In yet another embodiment, the present invention provides a method for reducing dc offset from a signal path in a receiver, comprising sampling the dc offset on the signal path at an output of a mixer, storing the offset signal on capacitive elements, feeding back the stored offset signal via a transconductance amplifier; adjusting a gain of the transconductance amplifier in response to variations in signal gain along the signal path; and subtracting the dc offset from the signal along the signal path.